The present invention relates to the supply of voltage to a non-volatile memory device and, more particularly, to a non-volatile memory device and a method of controlling a bulk voltage thereof, in which voltage applied to a bulk is controlled at the time of a program verification or read operation.
There is an increasing demand for non-volatile memory devices that can be electrically programmed and erased and that retain their data when power is off. In order to develop large-capacity memory devices capable of storing a large amount of data, highly-integrated memory cells have been developed. To this end, a NAND type flash memory device includes a plurality of memory cells connected in series to form one string. A plurality of the strings forms one memory cell array.
Flash memory cells of a NAND flash memory device include a current path formed between a source/drain region on a semiconductor substrate, and a floating gate and a control gate formed between insulating layers over the semiconductor substrate. A program operation of a flash memory cell is generally performed by grounding the source/drain region of a memory cell and a semiconductor substrate (that is, a bulk region) and applying a positive high voltage to the control gate to generate Fowler-Nordheim (F-N) tunneling between the floating gate and the substrate. In F-N tunneling, electrons of the bulk region are accumulated on the floating gate by an electric field of the high voltage applied to the control gate and, therefore, the threshold voltage of the memory cell is increased.
In recent years, in order to further increase the level of integration of the flash memory, active research has been made on a multi-bit cell that stores plural data in one memory cell. This type of a memory cell is generally called a multi-level cell (MLC). A memory cell of a single bit is called a single level cell (SLC).
FIG. 1A illustrates program threshold voltage distributions of a MLC.
Referring to FIG. 1A, the threshold voltage of a MLC that stores 2-bit data information shifts to one of four kinds of threshold voltage distributions in response to a program operation. It is assumed that the state 110 of a general cell illustrates a data state ‘11’. The state 110 is divided into threshold voltage distributions 120 indicating a data state ‘10’, threshold voltage distributions 130 indicating a data state ‘00’, and threshold voltage distributions 140 indicating a data state ‘01’ according to a program state.
Memory cells, programmed to have the threshold voltage distributions as shown in FIG. 1A, are erased on a per block basis. This block-based erase is represented as a shift of the following threshold voltage distributions.
FIG. 1B illustrates the shift of threshold voltage distributions due to an erase of a MLC.
Referring to FIG. 1B, in order to erase the memory cells programmed to have the threshold voltage distributions as shown in FIG. 1A, the threshold voltage distributions 120, 130 are first programmed so that they are changed to the threshold voltage distributions 140 having the highest level (S110).
After the memory cells shift to the threshold voltage distributions 140, an erase is performed on a per block basis (S120). If the erase is performed, the memory cells shift to the threshold voltage distributions 110.
Cells that have shifted to the threshold voltage distributions 110 or less of a desired erase cell (because the erase is performed too excessively according to the characteristics of memory cells) are subjected to a soft program and are included in the threshold voltage distributions 110 of FIG. 1B.
Program and erase operations as described above are repeatedly performed on memory cells of a flash memory device. As the number of cycles of erase and program operations is increased, the characteristics of the memory cells become degraded.